Verilog simulation x's in output -
i have problem verilog , cannot resolve it. tried different changes still no solution.
the code:
module perpetual_calender(); reg [3:0] year[277:0]; //14 different calendars can exist 2033-1755 = 288 years reg [2:0] month[3:0][3:0]; //different calenders combination of year , month reg [2:0] day [2:0][4:0]; //different days combination of calender , day of month. reg error; reg[0:3] c; reg[0:2] f, g; integer i,j; // fot year 0 = a, 1 = b... 13 = n task show_corresponding_day; input integer m; input integer d; input integer y; begin error = 0; $display("# (m/d/y) %d/%d/%d = ",m,d,y); if(y<1755 || y>2033 || m<1 || m>12 || d<1 || d>31) error = 1; if(!error) begin c = year[y-1755]; f = month[c][m]; $display("c = %d, f = %d", c, f); if(d > 29 + month[c][m+1] - (f+1)%7) error = 1; if(!error) g = day[f][d]; $display("g = %d", g); end case({error, g}) 4'd1: $display("monday\n"); 4'd2: $display("tuesday\n"); 4'd3: $display("wednesday\n"); 4'd4: $display("thrusday\n"); 4'd5: $display("friday\n"); 4'd6: $display("saturday\n"); 4'd7: $display("sunday\n"); default: $display("error\n"); endcase end endtask initial begin year[0] = 4'd2; for(i = 1756; i<=2033; i=i+1) begin if(year[i-1756] > 6) year[i-1755] = (year[i-1756]+2)%7; else year[i-1755] = (year[i-1756]+1)%7; j = i%4; if(i != 1800 && != 1900 && j == 0) year[i-1755] = year[i-1756]+7; end for(i = 0; i<7; i=i+1) begin month[i][1] = i; month[i][2] = (i+31)%7; month[i][3] = (month[i][2]+28)%7; month[i][4] = (month[i][3]+31)%7; $display("m = %b, n = %b\n", month[i][4], (month[i][3]+31)%7); month[i][5] = (month[i][4]+30)%7; month[i][6] = (month[i][5]+31)%7; month[i][7] = (month[i][6]+30)%7; month[i][8] = (month[i][7]+31)%7; month[i][9] = (month[i][8]+31)%7; month[i][10] = (month[i][9]+30)%7; month[i][11] = (month[i][10]+31)%7; month[i][12] = (month[i][11]+30)%7; month[i][13] = (month[i][12]+31)%7; // used in checking errors end for(i = 7; i<14; i=i+1) begin month[i][1] = i%7; month[i][2] = (i+31)%7; month[i][3] = (month[i][2]+29)%7; month[i][4] = (month[i][3]+31)%7; month[i][5] = (month[i][4]+30)%7; month[i][6] = (month[i][5]+31)%7; month[i][7] = (month[i][6]+30)%7; month[i][8] = (month[i][7]+31)%7; month[i][9] = (month[i][8]+31)%7; month[i][10] = (month[i][9]+30)%7; month[i][11] = (month[i][10]+31)%7; month[i][12] = (month[i][11]+30)%7; month[i][13] = (month[i][12]+31)%7; // used in checking errors end for(i = 0; <7; i=i+1) begin for(j=1; j<32; j=j+1) begin day[i][j] = (i+j-1)%7+1; end end show_corresponding_day(7,31,2001); show_corresponding_day(1,25,1987); show_corresponding_day(4,31,2008); show_corresponding_day(2,29,2005); show_corresponding_day(6,30,2013); show_corresponding_day(13,27,2013); show_corresponding_day(11,30,1001); show_corresponding_day(3,27,2012); end endmodule part of output:
# m = xxx, n = 00000000000000000000000000000110 # # m = xxx, n = 00000000000000000000000000000000 # # m = xxx, n = 00000000000000000000000000000001 # # m = xxx, n = 00000000000000000000000000000010 # # m = xxx, n = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx # # m = xxx, n = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx # # m = xxx, n = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx why or how x's in output? modules sum displays correctly output of register x.
the small example show issue:
module tb; reg [2:0] month[3:0][3:0]; initial begin month[0][2] = 3'b011; month[0][3] = (month[0][2]+28)%7; month[0][4] = (month[0][3]+31)%7; $display("2: %b", month[0][2]); $display("3: %b", month[0][3]); $display("4: %b", month[0][4]); end endmodule the problem have month[0][4] when definition reg [2:0] month[3:0][3:0];
you can address month[0][0] upto month[3][3], past out of range.
also note when run full code many array index out of bounds warnings due this.
you @ least want define: reg [2:0] month[6:0][13:1]; more common swap order of array bits ie:
reg [2:0] month[0:6][1:13];
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