vhdl - No feasible entries for infix operator "+" -

i designing 2s complement code showing error can 1 me that.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;  entity comp port(a : in std_logic_vector(7 downto 0);     y : out std_logic_vector(7 downto 0)); end comp;  architecture dataflow of comp signal temp: std_logic; begin     y<=  not(a) + "00000001"; end dataflow; 

error: d:/modelsim_projects/2scmpliment.vhd(13): no feasible entries infix operator "+".

when using synopsys packages, need add use of std_logic_unsigned package after std_logic_1164, like:

use ieee.std_logic_unsigned.all; 

with can use integer notation addition like:

y <= not(a) + 1; 

alternative use ieee vhdl standard numeric_std package, changes like:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ...   y <= std_logic_vector(unsigned(not(a)) + 1);