Use of << in given Verilog code? -
in following verilog code snippet implementing input buffer router, in second line, role of 1<<`buf_width ? understand << left shift operator, happens left shifting 1 `buf_width ? or there other function of << operator? `define buf_width 3 // buf_size = 16 -> buf_width = 4, no. of bits used in pointer `define buf_size ( 1<<`buf_width ) module fifo13( clk, rst, buf_in, buf_out, wr_en, rd_en, buf_empty, buf_full, fifo_counter ); input rst, clk, wr_en, rd_en; input [7:0] buf_in; // data input pushed buffer output[7:0] buf_out;// port output data using pop. output buf_empty, buf_full; // buffer empty , full indication output[`buf_width :0] fifo_counter; // number of data pushed in buffer reg[7:0] buf_out; reg buf_empty, buf_full; reg[`buf_width :0] fifo_counter; reg[`buf_width -1:0] rd_ptr, wr_ptr; // pointer read , write addresses reg[7:0] ...